Typically, during timing optimizing of a circuit design, the timing of the circuit design is not attempted to be improved beyond a specified value for the design, and the circuit design is not analyzed to determine the places in the design where potentials for optimization exist. It would be useful to more intelligently improve the timing of a circuit design.
Yield optimization of a circuit design is typically performed independently of timing optimization and often results in degradation of the timing obtained during timing optimization. It would be useful to more intelligently optimize the yield of a circuit design.
Thus, there is a need for improved timing and/or yield optimizations for a circuit design.